OmniScriptum Logic Synthesis : Register transfer level, Logic gates, Hardware Description Language, VHDL, Verilog, Bitstream Paperback

Please note that the content of this book primarily consists of articles available from Wikipedia or other free sources online. In electronics, logic synthesis is a process by which an abstract form of desired circuit behavior is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog. Some tools can generate bitstreams for programmable logic devices such as PALs or FPGAs, while others target the creation of ASICs. Logic synthesis is one aspect of electronic design automation. The roots of logic synthesis can be traced to the treatment of logic by George Boole, in what is now termed Boolean algebra. In 1938, Claude Shannon showed that the two-valued Boolean algebra can describe the operation of switching circuits. In the early days, logic design involved manipulating the truth table representations as Karnaugh maps. The Karnaugh map-based minimization of logic is guided by a set of rules on how entries in the maps can be combined. A human designer can typically only work with Karnaugh maps containing up to four to six variables.